Step analysis of the correct selection of MOS tube
The correct choice of MOS tube is a very important link. The poor selection of MOS tube may affect the efficiency and cost of the whole circuit. Understanding the nuances of different MOS tube components and the stress in different switching circuits can help engineers avoid many problems. Let's learn the correct selection method for the MOS tube.
The first step: choose N-channel or P-channel
The first step in choosing the right device for the design is to decide whether to use an N-channel or a P-channel MOS transistor. In a typical power application, when a MOS transistor is grounded and the load is connected to the mains voltage, the MOS transistor forms a low side switch. In low-side switches, N-channel MOSFETs should be used for consideration of the voltage required to turn the device off or on. When the MOS tube is connected to the bus and the load is grounded, the high side switch is used. P-channel MOS transistors are often used in this topology, which is also due to voltage drive considerations.
To choose the right device for your application, you must determine the voltage required to drive the device and the easiest way to do it in your design. The next step is to determine the required voltage rating or the maximum voltage the device can withstand. The higher the rated voltage, the higher the cost of the device. According to practical experience, the rated voltage should be greater than the mains voltage or bus voltage. This will provide sufficient protection so that the MOS tube will not fail. In the case of selecting a MOS transistor, it is necessary to determine the maximum voltage that can be withstood between the drain and the source, that is, the maximum VDS. It is important to know that the maximum voltage that a MOS tube can withstand changes with temperature. Designers must test the range of voltage variations over the entire operating temperature range. The rated voltage must have sufficient margin to cover this range of variation to ensure that the circuit does not fail. Other safety factors that design engineers need to consider include voltage transients induced by switching electronics such as motors or transformers. The rated voltages vary from application to application; typically, portable devices are 20V, FPGA power supplies are 20 to 30V, and 85 to 220VAC applications are 450 to 600V.
Step 2: Determine the rated current
The second step is to select the rated current of the MOS tube. Depending on the circuit configuration, this rated current should be the maximum current the load can withstand under all conditions. Similar to the voltage case, the designer must ensure that the selected MOS transistor can withstand this current rating, even when the system produces spike currents. The two considered current conditions are continuous mode and pulse spikes. In continuous conduction mode, the MOS transistor is in a steady state, at which point current continues through the device. A pulse spike is one in which a large amount of surge (or spike current) flows through the device. Once the maximum current under these conditions is determined, simply select the device that can withstand this maximum current.
After selecting the rated current, the conduction loss must also be calculated. In practical situations, the MOS tube is not an ideal device because there is a loss of power during the conduction process, which is called conduction loss. The MOS transistor acts like a variable resistor when it is "on", as determined by the RDS(ON) of the device and varies significantly with temperature. The power consumption of the device can be calculated from Iload2×RDS(ON). Since the on-resistance changes with temperature, the power consumption will also change proportionally. The higher the voltage VGS applied to the MOS transistor, the smaller the RDS(ON); otherwise the higher the RDS(ON). For system designers, this is where the trade-offs depend on the system voltage. For portable designs, it is easier (and more common) to use lower voltages, while for industrial designs, higher voltages can be used. Note that the RDS(ON) resistor will rise slightly with current. Various electrical parameter changes for RDS(ON) resistors can be found in the manufacturer's technical data sheet.
Need to remind the designer, in general, the Id current marked in the MOS tube specification is the maximum normal current of the MOS tube chip, and the maximum normal current in actual use is also limited by the maximum current of the package. Therefore, the maximum current setting for the customer when designing the product should take into account the maximum current limit of the package. It is recommended that the maximum current setting of the customer when designing the product is more important to consider the internal resistance parameters of the MOS.
Technology has a major impact on the characteristics of the device, as some techniques tend to increase RDS(ON) when increasing the maximum VDS. For such a technology, if it is intended to reduce VDS and RDS (ON), then it is necessary to increase the size of the wafer, thereby increasing the package size and associated development costs associated with it. There are several techniques in the industry that attempt to control the increase in wafer size, the most important of which are channel and charge balancing techniques.
In trench technology, a deep trench is embedded in the die, usually reserved for low voltage, to reduce the on-resistance RDS(ON). In order to reduce the impact of maximum VDS on RDS(ON), an epitaxial growth column/etch column process was used in the development process. For example, Fairchild has developed a technology called SupeRFET that adds additional manufacturing steps to the reduction of RDS(ON). This concern for RDS(ON) is important because as the breakdown voltage of a standard MOSFET increases, the RDS(ON) increases exponentially and causes the wafer size to increase. The SuperFET process turns the exponential relationship between RDS(ON) and wafer size into a linear relationship. In this way, SuperFET devices can achieve ideal low RDS(ON) in small wafer sizes, even at breakdown voltages up to 600V. The result is a wafer size that can be reduced by up to 35%. For the end user, this means a significant reduction in package size.
Step 3: Determine the thermal requirements
The next step in choosing a MOS tube is to calculate the thermal requirements of the system. Designers must consider two different situations, the worst case and the real situation. It is recommended to use the worst-case calculations because this result provides a greater margin of safety and ensures that the system does not fail. There are also some measurement data on the MOS tube data sheet; such as the thermal resistance between the semiconductor junction of the packaged device and the environment, and the maximum junction temperature.
The junction temperature of the device is equal to the maximum ambient temperature plus the product of thermal resistance and power dissipation (junction temperature = maximum ambient temperature + [thermal resistance x power dissipation]). According to this equation, the maximum power dissipation of the system can be solved, which is equivalent to I2 × RDS(ON) by definition. Since the designer has determined the maximum current to pass through the device, RDS(ON) at different temperatures can be calculated. It is worth noting that when dealing with simple thermal models, designers must also consider the thermal capacity of the semiconductor junction/device housing and the enclosure/environment; that is, the printed circuit board and package are not required to heat up immediately.
Avalanche breakdown refers to the reverse voltage on a semiconductor device exceeding a maximum value and forming a strong electric field to increase the current in the device. This current will dissipate power, increase the temperature of the device, and potentially damage the device. Semiconductor companies perform avalanche tests on devices, calculate their avalanche voltage, or test the robustness of the device. There are two ways to calculate the rated avalanche voltage; one is the statistical method and the other is the thermal calculation. The thermal calculation is widely used because it is more practical. In addition to calculations, technology also has a large impact on the avalanche effect. For example, an increase in wafer size will increase the resistance to avalanche, ultimately improving the robustness of the device. For the end user, this means using larger packages in the system.
Step 4: Determine switch performance
The final step in selecting the MOS tube is to determine the switching performance of the MOS tube. There are many parameters that affect the performance of the switch, but the most important are the gate/drain, gate/source and drain/source capacitances. These capacitors create switching losses in the device because they are charged every time they are switched. The switching speed of the MOS transistor is thus reduced, and the device efficiency is also lowered. To calculate the total loss of the device during the switching process, the designer must calculate the loss (Eon) during turn-on and the loss (Eoff) during turn-off. The total power of the MOSFET switch can be expressed by the following equation: Psw = (Eon + Eoff) × switching frequency. The gate charge (Qgd) has the greatest impact on switching performance.